Integrated circuits and methods for their fabrication

ABSTRACT

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation of internationalapplication PCT/US97/18979, with an international filing date of Oct.27, 1997, which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to integrated circuits, and moreparticularly to chip interconnection and to forming contact pads on theback side of a semiconductor chip, and also to thinning of integratedcircuits after circuit elements have been fabricated.

[0003] Some techniques for forming contacts on the chip “second” sideare disclosed in U.S. Pat. No. 5,270,261 issued Dec. 14, 1993 to Bertinet al. and entitled “Three Dimensional Multichip Package MethodsFabrication”. Alternative techniques are desired.

SUMMARY

[0004] The invention provides methods for making back-side contact padsin a semiconductor die (or “chip”). The back-side contact pads aresuitable for connecting the die to an underlying die to form a multi-dievertical integrated circuit. The invention also provides verticalintegrated circuits. In addition, the invention provides methods forthinning of individual dice whether or not the dice will be part of avertical integrated circuit.

[0005] In some embodiments of the present invention, back-side contactpads are formed as follows. A masked etch of the face side of asemiconductor wafer creates a via over each location where a back-sidecontact pad is to be formed. A dielectric is deposited over the via, anda conductive layer (for example, metal) is deposited over thedielectric. The bottom portion of the conductive layer in each via willform the back-side contact pad.

[0006] After the integrated circuit has been formed, the wafer is etchedfrom the back side until the back-side contact pad is exposed. The etchetches the wafer substrate faster than it etches the dielectricseparating the substrate from the pad. Therefore, the wafer substrate isreceded relative to the dielectric so that the dielectric protrudes downrelative to the substrate around each back-side contact pad. Thus thedielectric insulates the back-side contact pads from the substrate.

[0007] In some embodiments, the wafer is held by a non-contact waferholder during the back-side etch. The face side of the wafer does notphysically contact the holder. Therefore, there is no need to cover theface side with any protective layer to protect the wafer during theetch. Further, the holder protects the face side circuitry from theetch.

[0008] The wafer is diced into dice before or after the back-side etch.

[0009] In some embodiments, the back-side contact pads are used forvertical integration.

[0010] In some embodiments, the dice are not used for verticalintegration. The dice are thinned to reduce their vertical dimension.

[0011] Other embodiments and variations are within the scope of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIGS. 1-7, 8A and 8B are cross section illustrations of asemiconductor wafer in the process of fabrication of a back-side contactpad.

[0013]FIGS. 9 and 10 show three dice having back-side contact pads ofFIG. 8A; the dice are being connected together in a vertical integratedcircuit.

[0014] FIGS. 11-13 are cross-section illustrations of a semiconductorwafer in the process of creating a back-side contact pad.

[0015]FIGS. 14 and 15 each show three dice connected in a verticalintegrated circuit.

[0016]FIG. 16 illustrates the process and apparatus for thinning asemiconductor wafer by a back-side etch.

[0017]FIGS. 17 and 18 illustrate thinning of individual dice.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0018]FIG. 1 shows a wafer 104 a portion of which will provide a diehaving an integrated circuit with back-side contact pads. The back-sidecontact pads are suitable for connecting the die to an underlying die tocreate a “vertical integrated circuit”. The two dice will be stacked ontop of each other, reducing the lateral area taken by the circuit.

[0019] Wafer 104 includes silicon substrate 110. In some embodiments,the wafer has been processed to form transistors, capacitors, resistors,conductive lines, and/or other circuit elements, or portions of circuitelements, in, above and/or below substrate 110. In other embodiments, noportions of any circuit elements have been formed. The wafer thicknessis greater than the thickness of the die to be manufactured. In someembodiments, wafer 104 is 600-750 μm thick (dimension W is 600-750 μm).When the integrated circuit fabrication will be completed, the waferwill be thinned by an etch of the wafer back side 104B. The finalthickness of the die will be 100-350 μm or less in some embodiments.Other thicknesses are achieved in other embodiments. Providing a greaterwafer thickness at the beginning of fabrication makes the wafer strongerand thus increases the manufacturing yield.

[0020] FIGS. 1-3 show an etch of silicon substrate 110 on the wafer faceside to form vias in which the back-side contact pads will befabricated. As shown in FIG. 1, an aluminum layer 120 is deposited onsilicon 110. In some embodiments, the aluminum layer is 0.8-1.2 μmthick, 1 μm thick in some embodiments. Other thicknesses are used inother embodiments. Photoresist (not shown) is deposited and patterned.The aluminum 120 is etched to form an opening 124 exposing the silicon110. In some embodiments, aluminum 120 is etched by an acid dip. Inother embodiments, aluminum 120 is etched by a Cl-based vacuum plasmaetch described in “VLSI Electronic Microstructure Science”, the volume“Plasma Processing for VLSI” (edited by Norman G. Einspruch, AcademicPress, Inc. 1984), hereby incorporated herein-by reference. Otherauminum etches are used in other embodiments.

[0021] The width of opening 124 is shown as A. In some embodiments,opening 124 is round of a diameter A. In other embodiments, the openingis a square having a side A. Other opening shapes are used in otherembodiments. The center of the opening is located directly above thecenter of the corresponding back-side contact. The opening dimensionsare not greater than the dimensions of the back-side contact pad to beformed under the opening.

[0022] Other openings similar to opening 124 are formed simultaneouslyat the location of each back-side contact pad. Different openings mayhave different shapes and dimensions in the same wafer.

[0023] The photoresist is stripped, and silicon 110 is etched withaluminum 120 as a mask (FIG. 2). In some embodiments, the silicon etchis an isotropic vacuum plasma etch described in the aforementionedvolume “Plasma Processing for VLSI”. Other known etches are used inother embodiments. The etch forms vias 130 of a depth B at the locationof each back-side contact pad. Only one via 130 is shown in FIGS. 2 and3. The via depth B is at least as large as the final thickness of thedie to be manufactured. In some embodiments, the bottom side of via 130has the same shape and dimensions as the corresponding opening 124 inaluminum 120. The via widens as it goes up. As shown in FIG. 3, in someisotropic etch embodiments the dimensions of the top of via 130 arelarger by 2B than the respective dimensions of the bottom of the via. Inother embodiments, the top dimension is A+2C, where C≧0, e.g. 0≦C≦B. Ifthe etch is a perfectly anisotropic vertical etch (e.g. the horizontaletch rate is zero; this holds true for some known reactive ion etches),then C=0.

[0024] Aluminum 120 is removed by an acid dip or another method known inthe art (FIG. 3).

[0025] In some embodiments, the mask used in the etch of vias 130 ismade of a photoresist; aluminum is not used for the mask. However, insome embodiments in which the via depth B exceeds 20 μm, the mask isformed from aluminum or another material sufficiently resistant to thesilicon etch of vias 130.

[0026] A dielectric layer 140 (FIG. 4) is deposited over the wafer. Insome embodiments, layer 140 is undoped silicon dioxide and/or BPSG, 1-2μm thick, e.g. 1 μm thick. Other materials or thicknesses are used inother embodiments. In FIG. 4, layer 140 is BPSG formed by chemical vapordeposition at the atmospheric pressure. The distance between the top ofsilicon 110 and the bottom of vias 130 remains equal to B. Otherdeposition techniques, including thermal oxidation, are used in otherembodiments.

[0027] A conductive layer 150 (FIG. 5) is deposited over dielectric 140.In some embodiments, layer 150 is a 0.8-1.2 μm (e.g. 1 μm) layer ofaluminum, gold, or nickel; these metals can be deposited by vacuumsputtering. In other embodiments, layer 150 is some other metal or alloyused in VLSI for contact pads, for example, aluminum doped with siliconor copper or both. The thickness of layer 150 in one Al/Si/Cu embodimentis 0.8-1.2 μm. The bottom portions 150C of layer 150 in vias 130 willprovide the back-side contact pads.

[0028] The bottom portions 150C in vias 130 have about the samedimensions (such as A) as the respective openings 124 (FIG. 1).

[0029] A silicon dioxide glass layer 160 (FIG. 6) is deposited from TEOSand is spun on the wafer to fill the vias 130. Oxide 160 has a planartop surface. In some embodiments, no voids are left in the vias. Excessoxide 160 is etched off the wafer by a blanket etch so that the oxideremains in vias 130 but not outside the vias and the top surface of thewafer is planar.

[0030] Other materials and processes are used to fill vias 130 in otherembodiments.

[0031] Conductive layer 150 is patterned by standard photolithographictechniques to form conductive lines (not shown) connecting the back-sidecontact pads 150C in vias 130 to integrated circuit elements (formationof these elements may not yet be completed at this point).

[0032] In some embodiments, layer 150 is patterned at the stage of FIG.5 before the deposition of oxide 160 rather than after the deposition ofoxide 160. The photoresist mask (not shown) used to pattern metal 150protects the metal inside vias 130. After the patterning, the mask isremoved, and spin-on glass 160 is deposited from TEOS. Glass 160 is usedto planarize the wafer.

[0033] Then steps are performed to complete fabrication of theintegrated circuit, forming other circuit elements and, in particular,face side contact pads. In the embodiment of FIG. 7, these stepsinclude:

[0034] 1. Chemical vapor deposition of a dielectric layer 170 (silicondioxide, undoped and/or BPSG, 1 μm thick). Layer 170 is patterned ifneeded for circuit fabrication.

[0035] 2. Deposition of the last metal layer 180 (e.g. 0.8-1.2 μm ofAl/Si) over dielectric 170. Metal 180 is patterned to provide face sidecontact pads. In the embodiment of FIG. 7, one such pad 180C overlies aback-side pad 150C.

[0036] 3. Deposition of protective dielectric 190 (such as undopedsilicon dioxide and/or BPSG, 1 μm thick) over layer 180.

[0037] 4. Masked etch of dielectric 190 to expose the underlying contactpads in metal 180.

[0038] Then the wafer 104 back side is etched by an atmospheric pressureplasma etch described in O. Siniaguine, “Plasma Jet Etching atAtmospheric Pressure for Semiconductor Production”, 1996 1stInternational Symposium on Plasma Process-Induced Damage, May 13-14,1996, California, U.S.A., pages 151-153 hereby incorporated herein byreference. A suitable etcher is the plasma etcher of type “PLASM-AZ-05”described in “Plasma Jet Etching. Technology and Equipment. SiliconWafer Thinning & Isotropical Etching at Atmospheric Pressure” (AzCorporation, Geneva, Switzerland, SEMICON/EUROPA '95), April 1995. Seealso the following PCT publications incorporated herein by reference: WO96/21943 published Jul. 18, 1996; WO 92/12610 published Jul. 23, 1992;WO 92/12273 published Jul. 23, 1992. The plasma is a fluorine containingplasma maintained at the atmospheric pressure. The etch parameters areas follows: Ar (1 slm)+CF4 (3 slm) plasma in air ambient at atmosphericpressure. (“Slm” stands for standard liters per minute.) The DC power is12 kW. The wafer temperature is about 300° C. The silicon etch rate isabout 10 μm/min for an 8-inch wafer. Thus, a wafer can be etched from a720 μm thickness down to 120 μm in 1 hour. Alternatively, 1.6 wafers perhour can be etched from 720 μm down to 360 μm. The etch is illustratedin FIG. 16 described below.

[0039] This etch etches BPSG 140 about 10 times slower than silicon.

[0040] The etch does not etch the aluminum, gold or nickel in layer 150.

[0041] The resulting structure is shown in FIG. 8A. When silicon dioxide140 becomes exposed during the back-side etch, the etch etches silicondioxide 140 about 8-10 times slower than silicon 110. Therefore, whenthe silicon dioxide is etched off the back-side contact pads 150C, thebottom portions 140A, 140B of the silicon dioxide around the metal 150protrude down father than silicon 110. These protruding portions 140A,140B help insulate the silicon substrate 110 from metal 150. In someembodiments in which the oxide 140 is 1 μm thick, 10 μm of silicon isetched during the time during which 1 μm of oxide 140 is etched off theback-side contact pads 150C. Thus, the vertical dimension V ofprotruding oxide portions 140A, 140B is 8-10 μm (at least 9 μm in someembodiments), which is sufficient to insulate the back-side contact pads150C from the silicon substrate in some embodiments.

[0042] In some embodiments, oxide 140 is thicker, and the verticaldimension V of the protruding portions 140A, 140B left after exposingthe contact pads 150C is larger.

[0043] In some embodiments, the plasma processing continues to grow adielectric layer 192 (FIG. 8B) on the wafer backside. In particular,when the etch has been completed, the fluorine containing gas (forexample, CF₄) is turned off in the plasma reactor. Oxygen (or watervapor), or nitrogen, or both oxygen and nitrogen (for example, air), aresupplied with the plasma. The oxygen and/or nitrogen react to silicon110 to form silicon oxide (SiO or SiO₂), silicon nitride SiN_(x) (forexample, Si₃N₄), and/or oxy-nitride SiO_(x)N_(y).

[0044] In some embodiments, dielectric 192 is 0.01-0.02 μm thick toprovide reliable electrical isolation in a packaged vertical integratedcircuit powered by supply voltages below 5V.

[0045] In some embodiments of FIG. 8B, insulator 192 is grown at a wafertemperature of 300-500° C. The concentration of oxygen and/or nitrogenis 20-80%. In some embodiments using oxygen without nitrogen, theprocessing time is about 10 minutes to grow silicon oxide of a 0.02 μmthickness. The thickness of layer 192 can be increased by using higherwafer temperature, higher oxygen and/or nitrogen concentration, orlonger processing time.

[0046] In embodiments having the layer 192, metal 150 is chosen so asnot to form a non-conductive layer on its bottom surface during thelayer 192 fabrication. Thus, in some embodiments, metal 150 is gold,platinum, or some other metal that does not react with the species(oxygen or nitrogen) used to form layer 192. In other embodiments, metal150 is titanium, or some other metal, that forms a conductive layer (forexample, TiN) when the dielectric 192 is grown. In still otherembodiments, metal 150 is a stack of metal layers such that the bottomlayer of the stack does not form a non-conductive material on itssurface. For example, in some embodiments, the bottom layer is gold,platinum or titanium, and an overlying layer is aluminum.

[0047] Steps of fabrication of the integrated circuit elements can beintermixed with the back-side contact pad fabrication steps of FIGS.1-7, 8A, 8B in any suitable manner.

[0048] Then wafer 104 is diced into dice. FIGS. 9-10 show verticalinterconnection of three dice 200.1, 200.2, 200.3 which have beenobtained from wafers processed as in FIGS. 1-7, 8A, and possibly 8B(layer 192 is not shown in FIGS. 9-10 but is present in someembodiments). Different dice 200 may contain different integratedcircuits and may be obtained from different wafers 104. Suffix “.i”(i=1, 2, 3) in reference numerals in FIGS. 9-10 indicates correspondenceto the same numeral of FIGS. 1-7, 8A, 8B in die 200.i. For example,150C.3 denotes a back-side contact pad in die 200.3.

[0049] After the wafers are diced, a solder ball 210.(FIG. 9) is placedby a robot over each face-side contact pad in metal 180.i. Solder 210has a lower melting temperature than metal 150 or any other metalpossibly present in the dice. In some embodiments, solder 210.i is madeof tin, lead or their alloys. In some embodiments, the solder meltingtemperature is 120-180 degrees Celsius.

[0050] Some embodiments use conductive epoxy or conductive polymerinstead of solder.

[0051] The dice are aligned so that each back-side contact pad 150Cwhich is to be connected to an underlying die is positioned over therespective solder ball 210 in the underlying die. For example, contactpad 150C.3 is positioned over solder ball 210.2. In some embodiments,other dice (not shown) overly die 200.3 and underlie die 200.1. The diceare pressed together and heated. The heating temperature is sufficientto melt or soften the solder 210. The heating temperature is 120 to 180degrees C in some embodiments. The pressure is sufficient to create agood electrical contact between face-side pads in metal 180 and theoverlying back-side pads 150C. The force applied to press the waferstogether is 100-200 grams in some embodiments.

[0052] The dimensions of the solder 210 and the openings in dielectric190 that expose the face-side contact pads in metal 180 are chosen sothat the melted solder does not reach the lateral edges of the back-sidecontact pads 150C. For example, the melted solder 210.2 does not reachthe edge 150C.E.3 of contact pad 150C.3. The melted solder in contactwith the corresponding back-side contact pad 150C is held at the centerof the back-side contact pad by the surface tension force acting at theinterface between the solder and the pad. As a result, solder 210 doesnot contact the silicon 110 of the overlying wafer. The protrudingportions 140A, 140B (FIG. 8A) increase the distance between the exposedmetal 150 and the silicon 110. Since the solder adheres to the metal butnot to the oxide 140, the protruding portions 140A, 140B help to preventthe solder 210 from contacting the silicon 110. In the embodiments usingdielectric 192 (FIG. 8B), the dielectric 192 provides additionalprotection against silicon 110 contacting the solder.

[0053] Then the structure is cooled. The dice remain connected togetherin a vertical integrated circuit.

[0054] To strengthen the structure, the structure is placed in a vacuumchamber, and a dielectric adhesive 220 is introduced between the dice200 by methods known in the art. The adhesive fills the spaces betweenthe contacts formed by solder 210.

[0055]FIG. 10 shows the structure with back-side contact pads 150Cseated on solder 210. In some embodiments, the width W10 of each of theopenings in dielectric 190 that expose the face-side contact pads is 50to 100 μm. In some embodiments, each opening is round, and the openingwidth is the opening diameter. In other embodiments, the opening issquare, and its width is its side length. The width W11 of eachback-side contact pad 150C is 30-50 μm. The width is the diameter or theside length, as described above for the openings in dielectric 190. Thedistance D10 between the bottom surfaces of silicon substrates 110 ofadjacent dice is below 50 μm. The aspect ratio of each via 130 is below2:1 in some embodiments, and is about 1:1 in some embodiments. The lowaspect ratio increases the yield. The large width of openings indielectric 190 and of contact pads 150C, and hence the large area ofsolder connections, improves heat dissipation when local heating occurs.

[0056] The multi-die structure is then encapsulated into a plastic orceramic package, or some other package, using methods known in the art.

[0057] In FIGS. 11-13, the material 160 filling the vias 130 is metalrather than silicon dioxide. In FIG. 11, the wafer has been processed asshown in FIGS. 1-5. A metal ball 160 is placed by a robot into each via130 using a method known in the art. Alternatively, metal 160 isdeposited by electrodeposition. Before the electrodeposition process,the wafer face side is masked by a dielectric mask (not shown). The maskis made of photoresist in some embodiments. An opening is made in themask in the area of each via 130. Then electrodeposition is performed todeposit metal 160 into the vias through the openings. The mask is thenremoved. Other methods to deposit metal 160 are used in otherembodiments.

[0058] Metal 160 has a higher melting temperature than solder 210 (FIG.9) that will be used to make contacts between the dice. However, metal160 has a lower melting temperature than layer 150. Suitable metalsinclude tin (melting temperature 232° C.) , zinc (melting temperature420° C.), and their alloys. In some embodiments that use aluminum forinterconnects, the metal 160 melting temperature does not exceed 600° C.(the aluminum melting temperature is 660° C.).

[0059] In some embodiments, the volume of metal 160 in each via 130 isless than the volume of the via so that when the metal 160 melts, itwill not overflow its via.

[0060] The wafer is heated to melt the metal 160 (FIG. 12) withoutmelting the layer 150. In FIG. 12, the top surface of the metal filling160 is coplanar with, or below, the top surface of metal 150 outside thevia. In some embodiments, metal 160 overflows the vias and spreads overthe top surface of the wafer outside the vias.

[0061] Then any other circuit elements can be formed over the viasurface as shown in FIG. 13. In particular, in some embodiments, metallayer 150 is patterned to form conductive lines as described above forthe embodiment of FIG. 6. When the metal 150 is etched, any overlayingmetal 160 that may have overflowed the vias 130 is etched at the sametime.

[0062] Dielectric 170 (e.g. BPSG), last metal 180 (e.g. Al/Si) providingthe face-side contact pads, and dielectric 190 (e.g. BPSG; see FIG. 13)are deposited and photolithographically patterned similarly to theembodiment of FIG. 7. In some embodiments, metal 180 is aluminum depositby vacuum sputtering or thermal evaporation. The wafer temperatureduring deposition does not exceed 250-300° C. The wafer temperature doesnot exceed the melting temperature of metal 160.

[0063] The wafer is thinned as described above in connection with FIG.8A. In some embodiments, dielectric 192 is deposited as described abovein connection with FIG. 8B. In other embodiments, dielectric 192 isomitted. Then fabrication proceeds as shown above in FIGS. 9 and 10. Allthe processing steps of FIGS. 8A, 8B, 9, 10, including melting orsoftening the solder 210, are performed at temperatures below themelting temperature of metal 160.

[0064] Metal 160 increases the mechanical strength of the integratedcircuit. Metal 160 also improves heat dissipation when local heatingoccurs.

[0065] In FIG. 14, fillings 160 are omitted. After fabrication of thestructure of FIG. 5, dielectric 190 (BPSG in some embodiments) isdeposited directly on conductive layer 150. Dielectric 190 is removed invias 130 by a masked etch. The etch also removes dielectric 190 fromother selected areas of metal 150, such as area 150F, to form face-sidecontact pads away from vias 130.

[0066] The wafers are diced into dice. Solder balls 210 of a diameterlarger than the depth of vias 130 are placed in the vias. Solder is alsoplaced over those face-side contact pads 150F which are to be connectedto back-side contact pads 150C of overlying dice. Solder 210 in vias 130is sufficiently thick so that when the solder is melted or softened, thetop surface of the solder is at about the same height as the top surfaceof solder portions (not shown) over contacts 150F. The dice 200 arealigned, pressed together, and heated, as described above in connectionwith FIGS. 9-10. The solder melts or softens and creates contactsbetween adjacent dice.

[0067] In some embodiments, layer 190 of each die except the top diecontacts silicon substrate 110 or dielectric 192 (if present) of theadjacent overlying die. Adhesive is omitted in some embodiments sincefriction between layers 190 and silicon 110 or dielectric 192 createssufficient resistance to shearing forces.

[0068] The width W14 of each via 130 at the top is 90-150 μm in someembodiments. The width Wll of each back-side contact pad 150C is 30-50μm. The distance D14 between similar points on the adjacent dice, forexample, between bottom surfaces of substrates 110 of the adjacent dice,is 30-50 μm.

[0069] In FIG. 15, face-side contact pads do not overlie vias 130.Face-side contact pads 150F are made outside vias 130. Pads 150F aremade from Al/Si layer 150 as described above in FIG. 14, or from anothermetal layer. Fillings 160 are omitted in some embodiments, but arepresent in other embodiments. Solder balls 210 are placed in openings inBPSG 190 over contact pads 150F. The dice are aligned to position theback-side contact pads 150C over corresponding face-side contact pads150F. The dice are heated and pressed together as described above inconnection with FIGS. 9, 10 and 14. Solder 210 forms contacts betweenthe contact pads. Adhesive (not shown) is introduced in spaces betweenthe dice as described above in connection with FIGS. 9 and 10.Dielectric 192 (FIG. 8B) is present in some embodiments of FIG. 15 butnot in other embodiments.

[0070] In some embodiments, the die thickness T15 measured from the topsurface of dielectric 190 to the bottom surface of back-side contactpads 150C is 25 μm. Other thicknesses are used in other embodiments.

[0071]FIG. 16 illustrates the back-side plasma processing that includesthe etch exposing the contact pads 150C and (optionally) the depositionof dielectric 192. The processing is performed at atmospheric pressurein an etcher described above in connection with FIG. 8A. During the etchand deposition, the wafer 104 is held in a non-contact wafer holder1610. The wafer face side is oriented towards the holder 1610. Holder1610 holds the wafer from the top without physically contacting thewafer. See also the USSR inventor certificate 732198 of inventors A. F.Andreev and R. A. Luus, published May 8, 1980, and incorporated hereinby reference. Circular gas flow (vortex) 1614 between wafer holder 1610and wafer 104 holds the wafer up close to the holder, but does not allowthe wafer to contact the holder. Hence, a protective layer is not neededto protect circuitry 1618 on the wafer face side from physical contactwith the holder or from being etched or otherwise damaged by plasma jet1624. Plasma jet generator 1620 moves horizontally so that the plasmajet 1624 generated by the generator scans the wafer back side 104B.

[0072]FIG. 17-18 show an alternate atmospheric-pressure process suitablefor thinning the wafer. FIG. 17 consists of FIGS. 17A-17D. FIG. 17Aillustrates the wafer 104 right before the thinning process. Circuitry1618 has been fabricated on the wafer face side. In some embodiments,the wafer thickness is 600-720 μm. Silicon is removed from the waferback side by known methods (e.g. mechanical grinding) to reduce thewafer thickness to 150-350 μm. The resulting wafer is shown in FIG. 17B.The wafer is diced into chips 200 (FIG. 17C). The thickness of each chipis 150-350 μm. The chips are tested and sorted as known in the art. Thechips are thinned further by fluorine-containing plasma at atmosphericpressure, and (optionally) dielectric 192 is deposited on the back sideimmediately after the etch as shown in FIG. 18. The etcher and theprocess of FIG. 18 are similar to those of FIG. 16, but in FIG. 18 thenon-contact chip holder 1610 holds several individual chips (3 chips inFIG. 18) rather than a wafer. Each chip 200 is placed in an individualsegment of holder 1610 and is held in place by gas flow 1614 similarlyto FIG. 16. The plasma jet 1624 scans all the chips from the back sideuntil the dielectric 140 at the via bottoms is removed and (optionally)dielectric 192 is deposited. No protective layer for circuitry 1618 isneeded.

[0073] The atmospheric-pressure backside etch of the chips reduces thechip thickness to below 50 82 m (FIG. 17D).

[0074] Chips 200 can be stack packaged as described above in connectionwith FIGS. 10, 14, 15.

[0075] The two-stage process of FIG. 17 (e.g. mechanical groundingfollowed by plasma processing) reduces manufacturing costs in someembodiments. Indeed, depending on the manufacturing yield, the area ofthe wafer occupied by “bad” dice together with unused regions may beconsiderable, for example, 50% of the wafer. If the wafer is dicedbefore the thinning is completed as in the process of FIG. 17, and only“good” dice are thinned to completion and (optionally) provided withdielectric 192, time and resources are saved in thinning and depositionas compared to thinning the whole wafer and depositing dielectric 192over the whole wafer. Further, a wafer of a 6-8 inch diameter, thinneddown to 50 μm, is more fragile than a die having the same thickness butsmaller lateral dimensions (below 1 inch in some embodiments). This isanother reason why the manufacturing costs in some embodiments of FIG.17 are lower.

[0076] In some embodiments, the processes of FIGS. 16, 17 and 18 areused to thin wafers or dice that are not used in vertical integratedcircuits. In such embodiments, the back side etches may or may notexpose any conductive contacts. The processes of FIGS. 16-18 followfabrication of one or more circuit elements in or over the face side ofeach die or wafer. Therefore, the circuit element fabrication isperformed when the wafer is thicker than its final thickness and,therefore, is mechanically stronger.

[0077] The embodiments described above illustrate but do not limit theinvention. In particular, the invention is not limited by the number ofdice in a vertical integrated circuit (the number of dice can be anynumber greater than one), or by any particular thicknesses, openingwidths, or other dimensions. The invention is not limited by anyparticular materials. Non-silicon wafers are used in some embodiments.

1. A method for fabricating an integrated circuit, the methodcomprising: providing a body having one or more openings in a firstside; fabricating a first dielectric and a conductor in each of the oneor more openings with the conductor in each of the openings beingseparated from the body by the first dielectric; removing material froma second side of the body to expose the conductor in each of theopenings wherein the removing of the material comprises a process inwhich the removal rate of the first dielectric is lower than the removalrate of material of the body.
 2. The method of claim 1 wherein in saidprocess the removal rate of the first dielectric is about 10 times lowerthan the removal rate of the material of the body.
 3. The method ofclaim 1 wherein in said process the removal rate of the first dielectricis higher than the removal rate of the conductor.
 4. The method of claim1 wherein the removal of the material from the second side of the bodyis followed by forming a second dielectric on the second side of thebody but not on the conductor exposed on the second side.
 5. The methodof claim 1 wherein removing material from the second side comprisesplasma etching of the second side of the body at about an atmosphericpressure as the body is held in a non-contact holder.
 6. The method ofclaim 1 further comprising dicing the body before the removal of thematerial from the second side is completed, and removing material fromthe second side comprises removing material from individual dice.
 7. Themethod of claim 6 wherein removing material from the second sidecomprises: removing material from the second side before the body isdiced; and removing material from individual dice after the body isdiced.
 8. The method of claim 6 wherein removing material fromindividual dice is preceded by testing of the dice of the body, andremoving of the material from individual dice is performed only on a dieor dice that have passed the test.
 9. The method of claim 1 wherein thebody comprises semiconductor material.
 10. The method of claim 1 furthercomprising, after the removal of the material from the second side,connecting at least one integrated circuit of the body to one or moreother integrated circuits to form a vertical integrated circuit, with atleast one of the exposed conductors contacting a contact pad of anotherintegrated circuit.
 11. An integrated circuit comprising: asemiconductor body having one or more circuit elements formed in or overa first side of the body; one or more conductive contacts protrudingfrom a second side of the body, wherein at least one contact isconnected by one or more conductive lines to one or more circuitelements formed in or over the first side; and a dielectric separatingeach contact from the body, wherein the dielectric adjacent each contactprotrudes out of the semiconductor material of the second side aroundeach contact.
 12. The integrated circuit of claim 11 wherein thedielectric around each contact protrudes out of the semiconductormaterial of the second side by at least 8 μm measured in the directionperpendicular to the second side.
 13. The integrated circuit of claim 11further comprising dielectric that covers the second side of the circuitbut exposes the contact.
 14. The integrated circuit of claim 11 incombination with one or more other integrated circuits such that atleast one of the contacts contacts a conductive contact on anotherintegrated circuit, the combination forming a vertical integratedcircuit.
 15. A method for fabricating an integrated circuit, the methodcomprising: providing a body having one or more openings in a firstside; fabricating a first dielectric and a conductor in each of the oneor more openings so that the conductor in each of the openings isseparated from the body by the first dielectric; removing material froma second side of the body to expose the conductor in each opening; andforming a dielectric layer on the second side of the body by a processthat does not form a dielectric layer on the one or more contacts. 16.The method of claim 15 wherein forming the dielectric layer on thesecond side of the body comprises exposing the second side to a plasmacontaining a species that reacts with the material of the body to formthe dielectric layer but which does not form a dielectric on the one ormore contacts.
 17. A method for manufacturing a vertical integratedcircuit, the method comprising: manufacturing a plurality of individualintegrated circuits; after the manufacture of the individual integratedcircuits has been completed, and each individual integrated circuit hasbeen manufactured to its final thickness, attaching the individualintegrated circuits to each other to form a vertical integrated circuit.18. The method of claim 17 wherein manufacturing of the individualintegrated circuits comprises a back side etch of at least one of theindividual circuits as the circuit is held in a non-contact holder. 19.The method for integrated circuit fabrication, the method comprising:fabricating a plurality of integrated circuits from a semiconductorwafer, wherein the wafer with the integrated circuits is thicker thanthe final thickness of each integrated circuit; dicing the wafer intodice; and thinning one or more dice obtained from the wafer as the oneor more dice are held in a non-contact holder.
 20. The method of claim19 wherein fabricating a plurality of integrated circuits comprisesfabricating one or more circuit elements in or over a first side of thewafer, wherein each die has a first side which is part of the first sideof the wafer; and wherein during the thinning process, the first side ofeach of the one or more dice faces the non-contact holder which protectsone or more of the circuit elements fabricated in or over the firstsides of the one or more dice from being etched.
 21. The method of claim19 wherein the etching process comprises a fluorine containing plasmaetch at atmospheric pressure.
 22. The method of claim 19 wherein thewafer comprises silicon.
 23. The method of claim 19 wherein the thinningof the one or more dice is preceded by testing of the integratedcircuits, and the thinning is performed only on a die or dice that havepassed the test.